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| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2022-05-25 13:34:01 +0530 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-05-25 07:46:12 -0700 |
| commit | edd34368c4c3b45b1386b15f78b2229420f8c6d4 (patch) | |
| tree | 208a09fe9e2354b67ff0202cab5969f2c3fba4e6 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8ae664907916eba9a9d56296bed684c27318a872 (diff) | |
drm/i915/dg2: Support 4k@30 on HDMI
This patch adds a fix to support 297MHz of dot clock by calculating
the pll values using synopsis algorithm.
This will help to support 4k@30 mode for HDMI monitors on DG2.
v2: As per the algorithm, set MPLLB VCO range control bits to 3,
in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt)
v3: Fix typo. (Ankit)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220525080401.1253511-1-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions