diff options
| author | Wenjing Liu <wenjing.liu@amd.com> | 2021-11-02 12:43:47 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-11-22 14:45:01 -0500 |
| commit | ef9d5a54dae9be855352ead302a9659bb8610285 (patch) | |
| tree | 9230c5bce8661ef6c439d4b67e621533e9a2d6a9 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | fd3b2e21b8816273ca7813a8c9455c41ff77a96a (diff) | |
drm/amd/display: set MSA vsp/hsp to 0 for positive polarity for DP 128b/132b
[why]
There is a bug in MSA programming sequence that mistakenly set
MSA vsp/hsp to 1 for positive polarity. This is incorrect.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions