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| author | Kan Liang <kan.liang@linux.intel.com> | 2021-06-30 14:08:32 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-07-02 15:58:39 +0200 |
| commit | f57191edaaeb01279a88ace1be5b7230bdd8c0ab (patch) | |
| tree | ea97c25405d59638195a809af1d5ca0c43efee76 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 85f2e30f987ecc73fbb5e24eda0f36ba7f337c5c (diff) | |
perf/x86/intel/uncore: Add Sapphire Rapids server M2M support
The M2M blocks manage the interface between the mesh (operating on both
the mesh and the SMI3 protocol) and the memory controllers.
The layout of the control registers for a M2M uncore unit is a little
bit different from the generic one. So a specific format and ops are
required. Expose the common PCI ops which can be reused.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-9-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions