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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-04-07 20:16:24 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-04-14 10:58:14 +0200
commitf6462eb04f24447e3f9cc33071bbcb888f521985 (patch)
tree2d5566645af86dfa701efd32f413fb7b2afaa806 /tools/perf/scripts/python/export-to-sqlite.py
parent019b1a845404a97705726272d8a3ced6e78e592e (diff)
clk: renesas: rzv2h: Add support for RZ/V2N SoC
The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present only on the RZ/V2H(P) SoC. Add minimal clock and reset entries required to boot the Renesas RZ/V2N EVK and binds it with the RZ/V2H CPG family driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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