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| author | Richard Fitzgerald <rf@opensource.cirrus.com> | 2021-10-15 14:36:16 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-10-15 16:14:20 +0100 |
| commit | fdbd256175a1e11c1ba827112d56b9a3952e1219 (patch) | |
| tree | 356e66d37442d1a91e56a798f8646df28da768d4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 4ae1d8f911d6fc20baefd5eb061bf6964fa22a32 (diff) | |
ASoC: cs42l42: Set correct SRC MCLK
According to the datasheet the SRC MCLK must be as near as possible to
(125 * sample rate). This means it should be ~6MHz for rates up to 48k
and ~12MHz for rates above that. As per datasheet table 4-21.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211015133619.4698-14-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions