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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-07-24 22:34:28 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-07-28 13:51:42 -0400 |
| commit | 0a8735a6acf36ac35499563dc44f3e3d5034a2ce (patch) | |
| tree | e94f57ed33bae624ffbcaa50e636752a0b987bc8 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ce30d8b976b46b697cfcbc0aa5dab03edb0301dc (diff) | |
KVM: SVM: Do not virtualize MSR accesses for APIC LVTT register
AMD does not support APIC TSC-deadline timer mode. AVIC hardware
will generate GP fault when guest kernel writes 1 to bits [18]
of the APIC LVTT register (offset 0x32) to set the timer mode.
(Note: bit 18 is reserved on AMD system).
Therefore, always intercept and let KVM emulate the MSR accesses.
Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception")
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Message-Id: <20220725033428.3699-1-suravee.suthikulpanit@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions