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author | Miquel Raynal <miquel.raynal@bootlin.com> | 2024-12-24 18:05:54 +0100 |
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committer | Mark Brown <broonie@kernel.org> | 2025-01-09 20:16:30 +0000 |
commit | 13529647743d906ed3cf991f1d77727e7ff1fb6f (patch) | |
tree | 25dcad2ece9f841f9e8bc88b5b097a2c05f4f14e /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | 2438db5253eb17a7c0ccb15aea4252a150dda057 (diff) |
spi: microchip-core-qspi: Support per spi-mem operation frequency switches
Every ->exec_op() call correctly configures the spi bus speed to the
maximum allowed frequency for the memory using the constant spi default
parameter. Since we can now have per-operation constraints, let's use
the value that comes from the spi-mem operation structure instead. In
case there is no specific limitation for this operation, the default spi
device value will be given anyway.
This controller however performed a frequency check, which is also
observed during the ->check_op() phase.
The per-operation frequency capability is thus advertised to the spi-mem
core.
Cc: Conor Dooley <conor.dooley@microchip.com>
Cc: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-9-ad218dbc406f@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions