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authorChanho Park <chanho61.park@samsung.com>2022-05-04 16:51:46 +0900
committerSylwester Nawrocki <s.nawrocki@samsung.com>2022-05-10 19:19:34 +0200
commit17f7dc48aabd90a3327495dfc24c3476c43f12cb (patch)
treea94a8331105b0b198513e68fc9f4a617c98580d1 /tools/perf/scripts/python/exported-sql-viewer.py
parent6587c62f69dc11ca80ca746854626bf0394e1088 (diff)
clk: samsung: exynosautov9: add cmu_core clock support
Add CMU_CORE clock which represents Core BUS clocks. The source clocks of this CMU block are oscclk or dout_clkcmu_core_bus. Thus, two source clocks should be provided via device tree. All the gate clocks are defined as CLK_IS_CRITICAL because they control(gate/ungate) core bus clocks but not been assigned to any drivers. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-5-chanho61.park@samsung.com
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