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authorBjorn Helgaas <bhelgaas@google.com>2025-06-04 10:50:03 -0500
committerBjorn Helgaas <bhelgaas@google.com>2025-06-04 10:50:03 -0500
commit2ce738726adf934e272b3726de2df5843bc2e70c (patch)
tree1f510bc3c7c891feba92e7fb5aca3049852f5d0a /tools/perf/scripts/python/exported-sql-viewer.py
parent014dbfe0e402fe76cf2e4a0b21648c72c6ac4f8c (diff)
parentde0321bcc5fdd83631f0c2a6fdebfe0ad4e23449 (diff)
Merge branch 'pci/endpoint'
- For fixed-size BARs, retain both the actual size and the possibly larger size allocated to accommodate iATU alignment requirements (Jerome Brunet) - Simplify ctrl/SPAD space allocation and avoid allocating more space than needed (Jerome Brunet) - Correct MSI-X PBA offset calculations for DesignWare and Cadence endpoint controllers (Niklas Cassel) - Align the return value (number of interrupts) encoding for pci_epc_get_msi()/pci_epc_ops::get_msi() and pci_epc_get_msix()/pci_epc_ops::get_msix() (Niklas Cassel) - Align the nr_irqs parameter encoding for pci_epc_set_msi()/pci_epc_ops::set_msi() and pci_epc_set_msix()/pci_epc_ops::set_msix() (Niklas Cassel) * pci/endpoint: PCI: endpoint: Align pci_epc_set_msix(), pci_epc_ops::set_msix() nr_irqs encoding PCI: endpoint: Align pci_epc_set_msi(), pci_epc_ops::set_msi() nr_irqs encoding PCI: endpoint: Align pci_epc_get_msix(), pci_epc_ops::get_msix() return value encoding PCI: endpoint: Align pci_epc_get_msi(), pci_epc_ops::get_msi() return value encoding PCI: cadence-ep: Correct PBA offset in .set_msix() callback PCI: dwc: ep: Correct PBA offset in .set_msix() callback PCI: endpoint: pci-epf-vntb: Simplify ctrl/SPAD space allocation PCI: endpoint: Retain fixed-size BAR size as well as aligned size
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