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| author | Dan Williams <dan.j.williams@intel.com> | 2021-05-13 22:22:05 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-05-14 16:13:19 -0700 |
| commit | 399d34ebc2483c6091a587e5905c6ed34116fb05 (patch) | |
| tree | 87bbd3d1a38c1d6bc3974c31f9609defea07e386 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 5f653f7590ab7db7379f668b2975744585206b0d (diff) | |
cxl/core: Refactor CXL register lookup for bridge reuse
While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI
BAR, CXL root bridges have their MMIO base address described by platform
firmware. Refactor the existing register lookup into a generic facility
for endpoints and bridges to share.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162096972534.1865304.3218686216153688039.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions