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authorRobert Richter <rrichter@amd.com>2022-10-18 15:23:30 +0200
committerDan Williams <dan.j.williams@intel.com>2022-11-14 10:37:08 -0800
commit3bb80da51b1c1dbf31af2226f57cbc258f5e994b (patch)
treeae7eec7c7c62a07e7f6b198af38b6a04ab406bd8 /tools/perf/scripts/python/exported-sql-viewer.py
parentfa89248e669d589cdb895517e75cdead8d8ba5c0 (diff)
cxl/core: Check physical address before mapping it in devm_cxl_iomap_block()
The physical base address of a CXL range can be invalid and is then set to CXL_RESOURCE_NONE. In general software shall prevent such situations, but it is hard to proof this may never happen. E.g. in add_port_attach_ep() there this the following: component_reg_phys = find_component_registers(uport_dev); port = devm_cxl_add_port(&parent_port->dev, uport_dev, component_reg_phys, parent_dport); find_component_registers() and subsequent functions (e.g. cxl_regmap_to_base()) may return CXL_RESOURCE_NONE. But it is written to port without any further check in cxl_port_alloc(): port->component_reg_phys = component_reg_phys; It is then later directly used in devm_cxl_setup_hdm() to map io ranges with devm_cxl_iomap_block(). Just an example... Check this condition. Also do not fail silently like an ioremap() failure, use a WARN_ON_ONCE() for it. Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://lore.kernel.org/r/20221018132341.76259-3-rrichter@amd.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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