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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-02-11 10:56:03 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-18 10:34:14 +0100 |
| commit | 43961f7ee3f31c97209157bd19420ea8a65b1181 (patch) | |
| tree | 1d754f0f16a66b816d46815fc50d7919a9341bf3 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | a08903f0b0020cacf60b29d4708d7ebec5b041a4 (diff) | |
clk: renesas: rzv2h: Update error message
Update the error message in `rzv2h_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `GET_CLK_ON_OFFSET(reg)` offset and the
corresponding `clk` name (`%pC`). This enhances readability and aids
in debugging clock enable failures.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250211105603.195905-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions