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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-02 14:35:02 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:21 +0200 |
| commit | 53c58c08b454aea3c9c9ceda600567436134e6a2 (patch) | |
| tree | 7280388f2c583d2ac90ca29a10dc4f307a13098c /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 84c9829d16d86a09703d9f2c8dac3816c56bcdcd (diff) | |
clk: renesas: r9a07g044: Fix OSTM1 module clock name
Fix a typo in the name of the "ostm1_pclk" clock.
This change has no run-time impact.
Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions