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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-29 08:38:49 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 13:44:34 +0200 |
| commit | 549f4ae2601f968e2474c6031fb4799468882f64 (patch) | |
| tree | ac694c2d0e26212e1859276876384627dc240869 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | d5252d9697a3e7007c741e9c103073868955a304 (diff) | |
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL
for SD clock switching status.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions