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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-02 08:46:26 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 12:30:19 +0200 |
| commit | 59086e4193f4fc920a23d2045a473f62450b4269 (patch) | |
| tree | 89ccc4fd387dfa32c507ed096f795b7894e6762e /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | e11f804afc12e1c622f0a6f966fafd05b7022f8a (diff) | |
clk: renesas: r9a07g043: Add SDHI clock and reset entries
Add SDHI{0,1} mux, clock and reset entries to CPG driver
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions