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| author | Robert Richter <rrichter@amd.com> | 2023-06-22 15:55:11 -0500 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 12:22:53 -0700 |
| commit | 5d2ffbe4b81a3b6353bf888a523e7e5d4fec47ad (patch) | |
| tree | 536b1713da2cbbd90882e2d75a93de5cb97fda0c /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 19ab69a60e3ba58b4942b9ab5095cf90477a54ce (diff) | |
cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
Same as for ports, also store the downstream port's Component Register
mappings, use struct cxl_dport for that.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-16-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions