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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 14:21:59 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 14:21:59 +0200 |
| commit | 75b696a43fdd1740359cf967a6cbc9ae06fb616d (patch) | |
| tree | 935346030b86845af11f8008916212741ddde024 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | d70be079c3cf34bd91e1c8f7b4bc760356c9150c (diff) | |
| parent | a47b44fbb13f5e7a981b4515dcddc93a321ae89c (diff) | |
Merge tag 'clk-fixes-for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into renesas-dts-for-v6.7
Adding versa3 clock generator nodes to DTS depends on the fixed clock
index handling:
- Fix the binding for versaclock3 that was introduced this merge window
so we know what the values are for clk consumers
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions