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| author | Jerome Brunet <jbrunet@baylibre.com> | 2020-07-29 17:43:57 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-08-17 15:58:02 +0200 |
| commit | 7b70689b07c1d336a5ad6906927aa413619029bd (patch) | |
| tree | a5d91a61977290d5d6c78946c7d0b45a29b88994 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
clk: meson: add sclk-ws driver
This is yet another simple but odd driver for the audio block of the g12a
and sm1 SoC families.
For TDMOUT's sclk to be properly inverted, bit 29 of
AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28.
IOW bit28 == !bit29 at all times
This setting is automatically applied on axg and the manual setting was
added on g12a.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions