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| author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2023-08-07 11:21:44 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-08-21 18:40:37 +0530 |
| commit | 7bcdaa65810212c999d21e5c3019d03da37b3be3 (patch) | |
| tree | aa365d4e862c3e67cd6a466901682f7077f13351 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 491e9d409629964457d094ac2b99e319d428dd1d (diff) | |
dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit
AXIDMA IP in SG mode sets completion bit to 1 when the transfer is
completed. Read this bit to move descriptor from active list to the
done list. This feature is needed when interrupt delay timeout and
IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing
interrupt threshold.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/1691387509-2113129-6-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions