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| author | Matt Roper <matthew.d.roper@intel.com> | 2020-02-06 16:14:16 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2020-02-10 09:51:17 -0800 |
| commit | 9d5fd37ed7e26efdbe90f492d7eb8b53dcdb61d6 (patch) | |
| tree | 89c27f272b80b4bc01a4c33e5394920bb0dd3941 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ceaaf5300f881e54bba4221a710a40b48423f610 (diff) | |
drm/i915/ehl: Update port clock voltage level requirements
Voltage level depends not only on the cdclk, but also on the DDI clock.
Last time the bspec voltage level table for EHL was updated, we only
updated the cdclk requirements, but forgot to account for the new port
clock criteria.
Bspec: 21809
Fixes: d147483884ed ("drm/i915/ehl: Update voltage level checks")
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200207001417.1229251-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions