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| author | Badal Nilawar <badal.nilawar@intel.com> | 2023-09-20 14:36:20 +0530 |
|---|---|---|
| committer | Anshuman Gupta <anshuman.gupta@intel.com> | 2023-09-21 16:45:07 +0530 |
| commit | b17e6840882dc8a04e7464270906d79954378d41 (patch) | |
| tree | 50765bb60ab06014a3c6f4811f5e31869dda88ef /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 26a8e32e6d77900819c0c730fbfb393692dbbeea (diff) | |
drm/i915/gt: Update RC6 mask for mtl_drpc
It has been observed sometimes RC6 status register's unused bits are
being set by h/w, without affecting RC6 functionality therefore updating
the mask with used bits accordingly.
As mtl_drpc is debugfs function, removing MISSING_CASE from default case as
it doesn't make sense to panic (panic_on_warn=1) the CI system if register
is reporting unsupported state.
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230920090620.3255091-1-badal.nilawar@intel.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions