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| author | Devang Tailor <dev.tailor@samsung.com> | 2025-01-08 11:20:12 +0530 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-02-17 10:10:27 +0100 |
| commit | bbfc70ca7fd26ee3e7eb16872cf7b1f1be5907e3 (patch) | |
| tree | fbf2d819cca989c95cd6f70848ccc87a940a1882 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | f64fdd3c592dfb45d9c2be4b2506230467ebd27a (diff) | |
arm64: dts: exynosautov920: add CPU cache information
Add CPU caches information to its dt nodes so that the same is
available to userspace via sysfs. This SoC has 64/64 KB I/D cache and
256KB of L2 cache for each core, 2 MB of shared L3 cache for each quad
cpu cluster and 1 MB of shared L3 cache for the dual cpu cluster.
Signed-off-by: Devang Tailor <dev.tailor@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250108055012.1938530-1-dev.tailor@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions