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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-04-07 20:16:22 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-04-14 10:48:18 +0200
commitc04269c02273b24398590398c0b73605c72f17ac (patch)
treef473f8347509804cd6ee5aa75b8f2e32ef29b1b2 /tools/perf/scripts/python/exported-sql-viewer.py
parentdc7af24bd60bdced496d03473e67ce5eb51236a5 (diff)
dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
Document the device tree bindings for the Renesas RZ/V2N (R9A09G056) SoC Clock Pulse Generator (CPG). Update `renesas,rzv2h-cpg.yaml` to include the compatible string for RZ/V2N SoC and adjust the title and description accordingly. Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific clock driver will be reused for this SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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