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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-07-08 10:03:28 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-07-11 09:38:31 +0530 |
| commit | 3347b55f2c6c4bebc7a07343448416e5678b8b5c (patch) | |
| tree | 28dc84017002c62a1aa24231ee02028b0d679ebc /tools/perf/scripts/python/futex-contention.py | |
| parent | f7a9dc796567b2f1562f83373a5f134a20db25e9 (diff) | |
drm/i915/xe3lpd: Prune modes for YUV420
We only support resolution up to 4k for single pipe when using
YUV420 format so we prune these modes and restrict the plane size
at src. This is because pipe scaling will not support YUV420 scaling
for hwidth > 4096.
--v2
-Use output format to check [Ville]
-Add Bspec references
-Modify commit messge to point to why this is needed
--v3
-Use a function skl_scaler_mode_valid which is routed throug
intel_pfit_mode_valid [Ville]
-Combine the check conditons [Jonathan]
--v4
-mode_valid functions should return drm_mode_status [Jani]
--v5
-Use skl_scaler_max_src_size [Ankit]
Bspec: 49247, 50441
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> #v2
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250708043328.1086192-2-suraj.kandpal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions
