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| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2025-01-14 18:27:19 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-01-14 14:31:04 +0000 |
| commit | eab69050450ba63a4edb17d3d1a8654d2a130786 (patch) | |
| tree | a73c207146467676225b780be0353cdc05671597 /tools/perf/scripts/python/libxed.py | |
| parent | 9d499259db0cc5a31e212570c2cf945ad117b900 (diff) | |
ASoC: fsl_micfil: Add i.MX943 platform support
On i.MX943, the FIFO data address is changed to 0x20~0x3c,
compared to previous version, there is a minus 4 offset,
so add a new regmap configuration for it.
And the bit width of CICOSR is changed to 5 bits, from bit
16th to 20th in REG_MICFIL_CTRL2 register, so update its
definition header file.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/20250114102720.3664667-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
0 files changed, 0 insertions, 0 deletions