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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-08-12 18:17:20 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-08-20 09:16:32 +0200 |
| commit | 07e7ccd804dc2aac6f3f96129a86b02391b5002d (patch) | |
| tree | dcdd803c5e59d6d5bd29f585459499387cbd6709 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 54653bb3ec83d1f717adab6108db82a3966d19ee (diff) | |
clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
Add asynchronous core clocks and module clocks for SCI channels 1
through 5 on the RZ/T2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812171720.3245851-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions