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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-11 14:04:51 +0200 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-27 17:00:18 +0200 |
commit | dc643a843b5d510c04b2e222a1a4bd735d387f50 (patch) | |
tree | cce6fe4fd58e75f339f0dc6d8b2538b38cb06ed9 /tools/perf/scripts/python/mem-phys-addr.py | |
parent | b9d0b84b3db8552f033d5051393b90852b977a76 (diff) |
clk: renesas: r8a77990: Correct RCLK handling
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.
Hence change the OSC and RINT clock definitions to use the RCKCR
divider, and add the missing On-Chip Oscillator and RCLK clock source
switching logic.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions