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| author | Laura Nao <laura.nao@collabora.com> | 2025-09-15 17:19:27 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-09-21 09:35:57 -0700 |
| commit | e504d3bdb3d0bf581056f18ed12f7d2a59815cd1 (patch) | |
| tree | c09ebb829b91a0580ce96b49529c1e53f6f87cf9 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 8ceff24a754ac065123ae0ec9f31ec03aff55f8a (diff) | |
clk: mediatek: clk-gate: Add ops for gates with HW voter
MT8196 use a HW voter for gate enable/disable control. Voting is
performed using set/clr regs, with a status bit used to verify the vote
state. Add new set of gate clock operations with support for voting via
set/clr regs.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions