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| author | Denzeel Oliva <wachiturroxd150@gmail.com> | 2025-08-30 16:28:38 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-08-31 12:53:55 +0200 |
| commit | 19b50ab02eddbbd87ec2f0ad4a5bc93ac1c9b82d (patch) | |
| tree | cf8693657dcf839e75a08caff918a10f1a6e596d /tools/perf/scripts/python/netdev-times.py | |
| parent | e278e39b014d789fb670695d422ff33c3ef56040 (diff) | |
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
Parent select bits for shared PLLs are in PLL_CON0, not PLL_CON3.
Using the wrong register leads to incorrect parent selection and rates.
Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-1-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions