diff options
| author | Angelo Dureghello <adureghello@baylibre.com> | 2025-04-18 20:37:53 +0200 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2025-04-21 11:59:58 +0100 |
| commit | f083f8a21cc785ebe3a33f756a3fa3660611f8db (patch) | |
| tree | e4d554297a06feb7baf6b00fc33141d21b908974 /tools/perf/scripts/python/parallel-perf.py | |
| parent | ffcd19e9f4cca0c8f9e23e88f968711acefbb37b (diff) | |
iio: adc: ad7606: fix serial register access
Fix register read/write routine as per datasheet.
When reading multiple consecutive registers, only the first one is read
properly. This is due to missing chip select deassert and assert again
between first and second 16bit transfer, as shown in the datasheet
AD7606C-16, rev 0, figure 110.
Fixes: f2a22e1e172f ("iio: adc: ad7606: Add support for software mode for ad7616")
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Link: https://patch.msgid.link/20250418-wip-bl-ad7606-fix-reg-access-v3-1-d5eeb440c738@baylibre.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions