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author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-08-29 15:22:31 +0300 |
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committer | Thierry Reding <treding@nvidia.com> | 2025-09-11 18:28:35 +0200 |
commit | 7526e6db4703d0fe81b5397939c2aefd5fe8d9bc (patch) | |
tree | 9bcc33e7b071a024dafb5abd2233b88b68cce61e /tools/perf/scripts/python/sched-migration.py | |
parent | 669c71f6c6b0034f918430a2fdcf577683d31db6 (diff) |
dt-bindings: reset: Add Tegra114 CAR header
The way that resets are handled on these Tegra devices is that there is a
set of peripheral clocks & resets which are paired up. This is because they
are laid out in banks within the CAR (clock and reset) controller. In most
cases we're referring to those resets, so you'll often see a clock ID used
in conjection with the same reset ID for a given IP block.
In addition to those peripheral resets, there are a number of extra resets
that don't have a corresponding clock and which are exposed in registers
outside of the peripheral banks, but still part of the CAR. To support
those "special" registers, the TEGRA*_RESET() is used to denote resets
outside of the regular peripheral resets. Essentially it defines the offset
within the CAR at which special resets start. In the above case, Tegra114
has 5 banks with 32 peripheral resets each. The first special reset,
TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0 = 160.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions