diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2021-05-18 17:06:14 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2021-05-19 23:59:19 -0700 |
| commit | 14076e464550053527165aed352c7d9f4bf77e34 (patch) | |
| tree | 1e5a3d106de5316a7afa51c56d669dd0d525f8b4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 55ce306c2aa1aa2fd372e089e55a11a5512776cb (diff) | |
drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.
Bspec: 49213
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-7-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions