diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2021-05-18 17:06:22 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2021-05-19 23:59:31 -0700 |
| commit | 226c83263b10133c4f68ae6d39b1cf26e3d6b970 (patch) | |
| tree | 0f20a5c24c0efb870889f9823d9be1a50ffb4951 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ca962882268ac8d99ffe461c25522c68b1fdc39d (diff) | |
drm/i915/adl_p: Add PLL Support
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy cases.
Bspec: 55409,55316
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-15-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions