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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-03 19:55:58 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 10:03:07 +0100 |
| commit | 68f8eb19c18a377181622e58c1fd2ca0f5c0d15d (patch) | |
| tree | 45ebd93739584b37ca04191f51892f7aa3b242cc /tools/perf/scripts/python/stackcollapse.py | |
| parent | 1ab0a62f28c9347a5abb9ff9ba544271deb45f87 (diff) | |
arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes
Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103195600.23964-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions