diff options
| author | Angelo Dureghello <adureghello@baylibre.com> | 2024-10-08 17:43:33 +0200 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-10-15 18:59:50 +0100 |
| commit | 70602f529e4d76798c95aeed5ce2a8d36263abe5 (patch) | |
| tree | 6cb8da942fe004e4436805fd6d2ea2ed333bbb8d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 78134832a1f382b905d0fddd13148c9b8527c519 (diff) | |
iio: dac: adi-axi-dac: fix wrong register bitfield
Fix ADI_DAC_R1_MODE of AXI_DAC_REG_CNTRL_2.
Both generic DAC and ad3552r DAC IPs docs are reporting
bit 5 for it.
Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
Fixes: 4e3949a192e4 ("iio: dac: add support for AXI DAC IP core")
Cc: stable@vger.kernel.org
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Link: https://patch.msgid.link/20241008-wip-bl-ad3552r-axi-v0-iio-testing-v5-1-3d410944a63d@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions