diff options
| author | Peng Fan <peng.fan@nxp.com> | 2021-11-12 14:31:55 +0800 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2021-11-26 18:02:27 +0530 |
| commit | 7a0df1f969c14939f60a7f9a6af72adcc314675f (patch) | |
| tree | 370bca76a20c189fbfb626c526e6b6d4353f3d14 /tools/perf/scripts/python/stackcollapse.py | |
| parent | fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf (diff) | |
arm64: dts: ti: k3-j721e: correct cache-sets info
A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
- ICache is 3-way set-associative
- Dcache is 2-way set-associative
- Line size are 64bytes
So correct the cache-sets info.
Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions