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authorAviv Heller <avivh@mellanox.com>2018-08-23 13:47:53 +0300
committerSaeed Mahameed <saeedm@mellanox.com>2018-12-14 13:28:55 -0800
commit7c34ec19e10c0d13ca2f3435fb85d2dddccad917 (patch)
tree6eaceb0e3f8dc837c2f7346577376bcce011fdf9 /tools/perf/scripts/python/stackcollapse.py
parent292612d68c4ed3063cdc99512e865a819b8c9423 (diff)
net/mlx5: Make RoCE and SR-IOV LAG modes explicit
With the introduction of SR-IOV LAG, checking whether LAG is active is no longer good enough, since RoCE and SR-IOV LAG each entails different behavior by both the core and infiniband drivers. This patch introduces facilities to discern LAG type, in addition to mlx5_lag_is_active(). These are implemented in such a way as to allow more complex mode combinations in the future. Signed-off-by: Aviv Heller <avivh@mellanox.com> Reviewed-by: Roi Dayan <roid@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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