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| author | Samuel Holland <samuel@sholland.org> | 2023-01-26 00:34:17 -0600 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2023-01-27 23:20:30 +0100 |
| commit | 84def5abbb5252681bb5aa7e3e253c37b75ed9e7 (patch) | |
| tree | 1645f2bd19f159757aac7299573609a5b6ae24d4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 73b7d7f2dcf4f729028deec3f5e434af19270fda (diff) | |
dt-bindings: power: Add Allwinner D1 PPU
The Allwinner D1 family of SoCs contain a PPU power domain controller
separate from the PRCM. It can power down the video engine and DSP, and
it contains special logic for hardware-assisted CPU idle. Other recent
Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20230126063419.15971-2-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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