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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2025-01-26 13:46:04 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:06 +0100 |
| commit | 922c892834689939953c74bd34d01788b17feb7e (patch) | |
| tree | 6625eaa7e9d72b1bf18d88b57205a14421fca16f /tools/perf/scripts/python/stackcollapse.py | |
| parent | 90a2bee8a0c2889617d39e637547aa4728fcb43d (diff) | |
clk: renesas: r9a09g047: Add SDHI clocks/resets
Add SDHI[0-2] clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250126134616.37334-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions