diff options
| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2025-08-08 13:49:30 +0530 |
|---|---|---|
| committer | Gustavo Sousa <gustavo.sousa@intel.com> | 2025-08-13 11:13:02 -0300 |
| commit | 9465dd7c400d47439d3446de5b3f1ecfb5ea1bc6 (patch) | |
| tree | 8c14672b4834a1c84b2b591cec1590a699e1cb6a /tools/perf/scripts/python/stackcollapse.py | |
| parent | dcf101872d03a2394ed5f5aa5b2b036080285e3c (diff) | |
drm/i915/display: Add power well mapping for WCL
WCL has 3 pipes and two TC ports, create power well mapping to reflect
HW. Rest remains similar to Xe3 power well configuration.
v2: Remove TC3/4 ports as they do not exist.
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250808081931.4101388-1-chaitanya.kumar.borah@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions