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| author | Nishanth Menon <nm@ti.com> | 2021-11-12 22:36:35 -0600 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2021-12-03 17:18:37 +0530 |
| commit | a27a93bf70045be54b594fa8482959ffb84166d7 (patch) | |
| tree | dba132a63e585219ebea84b78451d12190294e1f /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3f92a5be6084b77f764a8bbb881ac0d12cb9e863 (diff) | |
arm64: dts: ti: k3-am642: Fix the L2 cache sets
A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
of 64 bytes and 16-way set-associative cache structure.
256KB of L2 / 64 (line length) = 4096 ways
4096 ways / 16 = 256 sets
Fix the l2 cache-sets.
[1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
[2] https://www.ti.com/lit/pdf/spruim2
Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions