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authorTony Lindgren <tony@atomide.com>2021-03-10 14:04:57 +0200
committerTony Lindgren <tony@atomide.com>2021-03-10 14:04:57 +0200
commita571cc394194543cc039ad92545e059a840a8e12 (patch)
tree85a319613bed7cd8a07376f45a1265f2ca1d08e0 /tools/perf/scripts/python/stackcollapse.py
parent41ccb6623711da26c5e6b34f3e05e271857bebb4 (diff)
ARM: dts: Move omap5 mmio-sram out of l3 interconnect
We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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