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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-17 01:12:46 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 10:52:21 +0100 |
| commit | a5c29f61466995d0d2c1370c709ef7fda534d386 (patch) | |
| tree | af6ab57805662192d81e26d731ed6724ff55803a /tools/perf/scripts/python/stackcollapse.py | |
| parent | e1a9faddffe7e555304dc2e3284c84fbee0679ee (diff) | |
arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes
Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117011247.27621-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions