diff options
| author | Manasi Navare <manasi.d.navare@intel.com> | 2021-05-25 17:06:55 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-05-26 06:46:37 -0700 |
| commit | bb265dbdf38d247064293de03996d7bcab40a68e (patch) | |
| tree | 5d26ffc3152758a299ae094241e40a78c2b15ed5 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 8bcc0840cf7ccf40db5e03cafe11c1cb28a0a73c (diff) | |
drm/i915/xelpd: Add VRR guardband for VRR CTL
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.
This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr enable functions. It also adds the corresponding
HW state readout for this field.
Bspec: 50508
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210526000656.3060314-3-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions