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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-25 10:52:40 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-28 16:37:44 +0200 |
| commit | be5b5fcbc779f04a6ad38e9d4772712fe05b6f15 (patch) | |
| tree | 787190745055ece2e120a85bdab7c039d84bc42d /tools/perf/scripts/python/stackcollapse.py | |
| parent | a9391e019015e96d4ed40587ce0f648edf1c32d3 (diff) | |
clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions