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| author | William Wu <william.wu@rock-chips.com> | 2023-12-26 15:19:59 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-01-02 14:35:23 +0100 |
| commit | ca2dc35e555e7043de585f4e46123d8fbd2b5a21 (patch) | |
| tree | 2df8e46a36e60d8967fe3b762543d8fcdbc5f020 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 9c6b789e954fae73c548f39332bcc56bdf0d4373 (diff) | |
usb: dwc2: Disable clock gating feature on Rockchip SoCs
The DWC2 IP on the Rockchip SoCs doesn't support clock gating.
When a clock gating is enabled, system hangs.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Minas Harutyunyan <hminas@synopsys.com>
Link: https://lore.kernel.org/r/1703575199-23638-1-git-send-email-william.wu@rock-chips.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions