diff options
| author | Lo-an Chen <lo-an.chen@amd.com> | 2025-08-25 18:16:24 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-09-23 10:27:01 -0400 |
| commit | f082daf08f2ff313bdf9cf929a28f6d888117986 (patch) | |
| tree | e16134f94837e3e71e13cd03841979f774352afa /tools/perf/scripts/python/stackcollapse.py | |
| parent | 6cec25f5b5660602b1953038cf40968b2d71c403 (diff) | |
drm/amd/display: Init dispclk from bootup clock for DCN314
[Why]
Driver does not pick up and save vbios's clocks during init clocks,
the dispclk in clk_mgr will keep 0 until the first update clocks.
In some cases, OS changes the timing in the second set mode
(lower the pixel clock), causing the driver to lower the dispclk
in prepare bandwidth, which is illegal and causes grey screen.
[How]
1. Dump and save the vbios's clocks, and init the dispclk in
dcn314_init_clocks.
2. Fix the condition in dcn314_update_clocks, regarding a 0kHz value.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Lo-an Chen <lo-an.chen@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
