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| author | Imre Deak <imre.deak@intel.com> | 2023-06-06 20:28:22 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2023-06-20 13:45:59 +0300 |
| commit | f4e498eb1247d25231198856b57bbae00f403c85 (patch) | |
| tree | 1aa09fb94cfbf16c9c8e91065907f8ea888adc3b /tools/perf/scripts/python/stackcollapse.py | |
| parent | 783d8b80871f6014a5c73182f63e1ec3c6bdfcd2 (diff) | |
drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionality
A recent bspec update added a restriction on when DC states can be enabled:
[Before enabling DC states:]
"""
PG2 can be kept enabled only because PGB requires PG2.
Do not use PG2 functions, such as type-C DDIs.
DMC will dynamically control PG1, PGA, PG2, PGB.
"""
Accordingly prevent DC states if PW2 (aka PG2) is enabled for any other
functionality.
Bpsec: 49193
Fixes: 88c487938414 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2")
Reported-by: Kai Vehmanen <kai.vehmanen@intel.com>
Tested-by: Ambica Pramod <ambica.pramod@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606172822.1891897-1-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions