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authorBiju Das <biju.das.jz@bp.renesas.com>2025-07-30 17:46:14 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2025-08-19 14:34:14 +0200
commit74f44ad07d1063933c237a7db16f6a4036643d60 (patch)
tree3fa3ea7d39e01b2b8c3d2da562499c09f18ff305 /tools/perf/scripts/python/stat-cpi.py
parent9c174e4dacee9fb2014a4ffc953d79a5707b77e4 (diff)
mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64 bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes. During testing it is found that, if the DMA buffer is not aligned to 128 bit it fallback to PIO mode. In such cases, 64-bit access is much more efficient than the current 16-bit. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250730164618.233117-2-biju.das.jz@bp.renesas.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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