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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2022-11-13 22:12:46 +0300
committerLorenzo Pieralisi <lpieralisi@kernel.org>2022-11-23 16:01:54 +0100
commit875596361910711f3e7ba6314075d867e4b74fd1 (patch)
tree46c51547bd97adf30f9abc97cb211a6a1ec360fa /tools/perf/scripts/python/stat-cpi.py
parentb9fe9985aee2cb62814671b883b9cbfa1c941ab3 (diff)
dt-bindings: PCI: dwc: Add phys/phy-names common properties
It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit PHY phandle references. There can be up to 16 PHYs attach in accordance with the maximum number of supported PCIe lanes. Let's extend the common DW PCIe controller schema with the 'phys' and 'phy-names' properties definition. There two types PHY names are defined: preferred generic names '^pcie[0-9]+$' and non-preferred vendor-specific names '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6; "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d": keystone, dra7xx; "pcie": histb, etc). Link: https://lore.kernel.org/r/20221113191301.5526-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
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